Techniques for transient fault sensitivity analysis and reduction in VLSI circuits

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn 2003-January, Issue , 2003, Pages 597-604

  Maheshwari, Atul ^a   Koren, Israel ^a   Burleson, Wayne ^a  

^a University of Massachusetts   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC NETWORK ANALYSIS; FAULT TOLERANCE; FAULT TREE ANALYSIS; RECONFIGURABLE HARDWARE; SENSITIVITY ANALYSIS;

BINARY COUNTERS; CIRCUIT LEVELS; COMPUTATIONAL COSTS; FAULT SENSITIVITY; RANDOM SIMULATION; TECHNOLOGY SCALING; TRANSIENT FAULTS;

VLSI CIRCUITS;

EID: 84964963367     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/TSM.2005.1250160     Document Type: Conference Paper

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