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Volumn 1, Issue , 2004, Pages 175-179

Emerging challenges of underfill for flip chip application

Author keywords

[No Author keywords available]

Indexed keywords

CONTACT ANGLE; DIES; ELECTRIC POWER UTILIZATION; ELECTRONICS PACKAGING; FILLERS; FRACTURE TOUGHNESS; LEAD ALLOYS; PASSIVATION; SILICON; SOLDERING ALLOYS; SURFACE TENSION;

EID: 10444268074     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (19)

References (20)
  • 1
    • 0037004425 scopus 로고    scopus 로고
    • Underfill viscous flow between parallel plates and solder bumps
    • Dec.
    • Wen-Bin Young and Wen-Lin Yang, "Underfill Viscous Flow between Parallel Plates and Solder Bumps", IEEE Trans. Comp. Packag. Technol., Vol. 25, No. 4, pp. 695-700, Dec., 2002.
    • (2002) IEEE Trans. Comp. Packag. Technol. , vol.25 , Issue.4 , pp. 695-700
    • Young, W.-B.1    Yang, W.-L.2
  • 2
    • 0031276349 scopus 로고    scopus 로고
    • Analysis of the flow encapsulant during underfill encapsulation of flip chip
    • Nov.
    • S. Hanand K. K. Wang, "Analysis of the Flow Encapsulant during Underfill Encapsulation of Flip Chip", IEEE Trans. Comp., Packag., Manufact. Technol., B, Vol. 20, pp. 424-433, Nov., 1997.
    • (1997) IEEE Trans. Comp., Packag., Manufact. Technol., B , vol.20 , pp. 424-433
    • Hanand, S.1    Wang, K.K.2
  • 3
    • 0036881383 scopus 로고    scopus 로고
    • The effect of solder bump pitch on the underfill flow
    • Dec.
    • Wen-Bin Young and Wen-Lin Yang, "The Effect of Solder Bump Pitch on the Underfill Flow", IEEE Trans. Advan. Packag., Vol. 25, No. 4, pp. 537-542, Dec., 2002.
    • (2002) IEEE Trans. Advan. Packag. , vol.25 , Issue.4 , pp. 537-542
    • Young, W.-B.1    Yang, W.-L.2
  • 4
    • 0041528348 scopus 로고    scopus 로고
    • Preparation and thermal properties of epoxy-silica nanocomposites from nanoscale colloidal silica
    • Y.-L. Liu, C.-Y. Hsu, W.-L. Wei, R.-J. Jeng, "Preparation and Thermal Properties of Epoxy-Silica Nanocomposites from Nanoscale Colloidal Silica", Polymer, 44, pp 5159-5167, 2003
    • (2003) Polymer , vol.44 , pp. 5159-5167
    • Liu, Y.-L.1    Hsu, C.-Y.2    Wei, W.-L.3    Jeng, R.-J.4
  • 6
    • 10444257168 scopus 로고    scopus 로고
    • The effect of flow properties on filler settling of underfill in flip chip package
    • to be published in June
    • Jinlin Wang and Tim Chen, "The Effect of Flow Properties on Filler Settling of Underfill in Flip Chip Package", to be published in Proc. Electronic Components and Technology Conference, June 2004
    • (2004) Proc. Electronic Components and Technology Conference
    • Wang, J.1    Chen, T.2
  • 8
    • 0003621055 scopus 로고
    • New York: Van Nostrand Reinhold
    • J. H. Lau, Chip on Board. New York: Van Nostrand Reinhold, 1994
    • (1994) Chip on Board
    • Lau, J.H.1
  • 10
    • 10444269718 scopus 로고    scopus 로고
    • Underfill-induced stresses in flip chip assemblies
    • to be published June
    • J. M. Hurley and T. L. Berfield, "Underfill-induced stresses in flip chip assemblies", to be published in ECTC, June 2004
    • (2004) ECTC
    • Hurley, J.M.1    Berfield, T.L.2
  • 11
    • 33745946870 scopus 로고    scopus 로고
    • Measurement of backside flip chip die stresses using piezoresistive test die
    • Chicago, IL, Oct. 26-28
    • J. C. Suhling et. al., "Measurement of Backside Flip Chip Die Stresses Using Piezoresistive Test Die", Proc. IMAPS'99, Chicago, IL, Oct. 26-28, 1999
    • (1999) Proc. IMAPS'99
    • Suhling, J.C.1
  • 12
    • 10444266853 scopus 로고    scopus 로고
    • Development of low stress materials for low-K copper integrated circuit packaging
    • San Diego, CA, May
    • M. Todd, L. Crane, G. Carson, J. Zhang, "Development of low stress materials for low-K copper integrated circuit packaging", Proc. IMAPS Advanced Technology Workshop, San Diego, CA, May 2003
    • (2003) Proc. IMAPS Advanced Technology Workshop
    • Todd, M.1    Crane, L.2    Carson, G.3    Zhang, J.4
  • 13
    • 10444249148 scopus 로고    scopus 로고
    • Flip chip underfill technology development for next generation silicon technologies
    • to be published June
    • K. Nagarajan, K. Desai, M. Todd, G. Carson, "Flip chip underfill technology development for next generation silicon technologies", to be published in ECTC, June 2004
    • (2004) ECTC
    • Nagarajan, K.1    Desai, K.2    Todd, M.3    Carson, G.4
  • 15
    • 0033352434 scopus 로고    scopus 로고
    • Recent advances in the development of no-flow underfill encapsulants - A practical approach towards the actual manufacturing application
    • S. H. Shi, C. P. Wong, "Recent advances in the development of no-flow underfill encapsulants - a practical approach towards the actual manufacturing application", IEEE Transaction on Electronics Packaging Manufacturing, Vol. 22, 1999, pp. 331-339
    • (1999) IEEE Transaction on Electronics Packaging Manufacturing , vol.22 , pp. 331-339
    • Shi, S.H.1    Wong, C.P.2
  • 17
    • 10444290944 scopus 로고    scopus 로고
    • NO-flow underfill: A reliability and failure mode analysis
    • San Diego, CA, Jan.
    • M. Previti, "NO-flow underfill: a reliability and failure mode analysis", Proc. APEX, San Diego, CA, Jan. 2001, pp. MT2-1 1-5
    • (2001) Proc. APEX
    • Previti, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.