Multi-level approach for high-precision cache fault isolation - Case study: Itanium® II processor low voltage cache yield improvement

Proceedings of the 30th International Symposium for Testing and Failure Analysis, ISTFA 2004

Volumn , Issue , 2004, Pages 498-505

  Kong, Chia Ling ^a   Islam, Mohammed R ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COMPUTER SIMULATION; DEFECTS; DESIGN FOR TESTABILITY; INTEGRATED CIRCUITS; LIQUID CRYSTALS; MICROPROCESSOR CHIPS; STATIC RANDOM ACCESS STORAGE;

CACHE FAULT ISOLATION METHODOLOGY; CIRCUIT SIMULATION; EMISSION MICROSCOPY; PHYSICAL FAILURE ANALYSIS (PFA);

FAILURE ANALYSIS;

EID: 10444267418     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Egger, P. et al, "SRAM failure analysis strategy", Conf. Proc. of the 29th International Symposium for Testing and Failure Analysis, (2003), pp. 177-83.
2. Schienle, M. et al, "Improved SRAM failure diagnosis for process monitoring via current signature analysis", 10th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis, ESREF (1999), vol.39, pp 1009-14
3. Chinnaswamy, Kumar K. et al, "Design of Cache LYA Access Under High Leakage Process Technology", Design and Test Technology Conference, DTTC, (2001), pp 1-7
4. Wong, V. K. et al, "Electrical Analysis to Fault Isolate Defects in 6T Memory Cells", Proc 9th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA (2002), pp. 101-104
5. Song, Z. et. al., "Open contact analysis of single bit failure in 0.18 mu technology", Microelectronics Reliability, vol.42, no.12, Dec. 2002, pp. 1997-2001.