SRAM Failure Analysis Strategy

Conference Proceedings from the International Symposium for Testing and Failure Analysis

Volumn 2003-November, Issue , 2003, Pages 177-183

  Egger, P ^a   Burmer, C ^a  

^a INFINEON TECHNOLOGIES AG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CRYSTAL STRUCTURE; LIQUID CRYSTALS;

ANALYSIS STRATEGIES; EMISSION MICROSCOPY; LIQUID-CRYSTALS; LOCALISATION; LOGIC IC; METAL LAYER; SRAM FAILURES; STRUCTURE SIZES;

FAILURE ANALYSIS;

EID: 10444251639     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.31399/asm.cp.istfa2003p0177     Document Type: Conference Paper

References (4)

1. J.-Y. Glacet, F. Lee : Embedded SRAM Bitmapping and Failure Analysis for Manufacturing Yield Improvement, Proc. of the 26th. ISTFA 2000
2. C. Brillert et. al. : SRAM Failure Analysis Flow, Proc. of the 27th. ISTFA 2001
3. Kinoshata, K. and Saluja, Built-in Testing of Memory using on-chip compact testing scheme, Proc. Of IEEE International Test Conference (1984)
4. R. Kunin A.J. van de Gore, Testing Semiconductor Memories, ComTex Publishing, Gouda, The Netherlands, (1998)