Electrical analysis to fault isolate defects in 6T memory cells

Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

Volumn 2002-January, Issue , 2002, Pages 101-104

  Wong, V K ^a   Lock, C H ^a   Siek, K H ^a   Tan, P J ^a  

^a Intel Technology Malaysia Sdn Bhd   (Malaysia)

Author keywords

Circuit analysis; Circuit faults; Circuit testing; Design for testability; Failure analysis; Microprocessors; Optical device fabrication; Random access memory; Spatial resolution; Turning

Indexed keywords

CELLS; CYTOLOGY; DEFECTS; DESIGN FOR TESTABILITY; ELECTRIC NETWORK ANALYSIS; INTEGRATED CIRCUITS; MEMORY ARCHITECTURE; MICROPROCESSOR CHIPS; RANDOM ACCESS STORAGE; SEMICONDUCTOR STORAGE; STATIC RANDOM ACCESS STORAGE; TURNING;

CIRCUIT FAULTS; CIRCUIT TESTING; OPTICAL DEVICE FABRICATION; RANDOM ACCESS MEMORY; SPATIAL RESOLUTION;

FAILURE ANALYSIS;

EID: 51949083580     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPFA.2002.1025622     Document Type: Conference Paper

References (3)

1. Y.W. Lim and T.S. Yeoh, "Novel Cell Isolation Technique for the Analysis of CMOS SRAM Cell Cold Failure", in International Conference on Semiconductor Electronics, 1998
2. th International Symposium for Testing and Failure Analysis, 2001
3. th VLSI Test Symposium, 1997