50-Gbit/s InP HEMT 4:1 multiplexer/1:4 demultiplexer chip set with a multiphase clock architecture

IEEE Transactions on Microwave Theory and Techniques

Volumn 51, Issue 12, 2003, Pages 2548-2554

  Sano, Kimikazu ^a   Murata, Koichi ^a   Kitabayashi, Hiroto ^a   Sugitani, Suehiro ^a   Sugahara, Hirohiko ^a   Enoki, Takatomo ^a  

^a NTT CORPORATION   (Japan)

Author keywords

1:4 demultiplexer (DMUX); 4:1 multiplexer (MUX); InP high electron mobility transistor (HEMT); Multiphase clock (MPC); OC 768; Optical communication systems; STM 256

Indexed keywords

DEMULTIPLEXING; ELECTRIC POWER SUPPLIES TO APPARATUS; FLIP FLOP CIRCUITS; HIGH ELECTRON MOBILITY TRANSISTORS; MULTIPLEXING EQUIPMENT; OPTICAL COMMUNICATION; SEMICONDUCTING INDIUM PHOSPHIDE; TIME DIVISION MULTIPLEXING; TIMING CIRCUITS;

DEMULTIPLEXER; MULTIPHASE CLOCK ARCHITECTURE; MULTIPLEXER; POWER CONSUMPTION;

MICROPROCESSOR CHIPS;

EID: 0742304084     PISSN: 00189480     EISSN: None     Source Type: Journal    
DOI: 10.1109/TMTT.2003.819205     Document Type: Article

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