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Volumn 51, Issue 1, 2004, Pages 14-19

A CMOS-compatible rapid vapor-phase doping process for CMOS scaling

Author keywords

CMOS process; Doping; Junction; MOSFET

Indexed keywords

ELECTRIC CURRENTS; MOSFET DEVICES; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DOPING;

EID: 0742286726     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.820643     Document Type: Article
Times cited : (6)

References (13)
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  • 6
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  • 7
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    • Phosphorus direct doping from vapor phase into silicon for shallow junctions
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  • 8
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  • 13
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    • A possible mechanism for reconciling large gate-drain overlap capacitance with a small difference between polysilicon gate length and effective channel length in an advanced technology PFET
    • July
    • R. Young, L. Su, M. Ieong, and S. Kapur, "A possible mechanism for reconciling large gate-drain overlap capacitance with a small difference between polysilicon gate length and effective channel length in an advanced technology PFET," IEEE Electron Device Lett., vol. 19, pp. 234-236, July 1998.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.