A possible mechanism for reconciling large gate-drain overlap capacitance with a small difference between polysilicon gate length and effective channel length in an advanced technology PFET

IEEE Electron Device Letters

Volumn 19, Issue 7, 1998, Pages 234-236

  Young, R ^a   Su, L ^a   Ieong, M ^a   Kapur, S ^a  

^a IBM MICROELECTRONICS   (United States)

Author keywords

Capacitance; CMOSFET logic devices; Semiconductor process modeling; Semiconductor insulator interfaces; Simulation

Indexed keywords

CAPACITANCE; DOPING (ADDITIVES); FIELD EFFECT TRANSISTORS; GATES (TRANSISTOR); LOGIC DEVICES; MODELS; SIMULATION;

GATE LENGTHS;

CMOS INTEGRATED CIRCUITS;

EID: 0032122855     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/55.701427     Document Type: Article

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