Synchronous mirror delay for multiphase locking

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 1, 2004, Pages 150-156

  Yoon, Yong Jin ^a   Kwon, Hyuck In ^b   Lee, Jong Duk ^b   Park, Byung Gook ^b   Kim, Nam Seong ^a   Cho, Uk Rae ^a   Byun, Hyun Guen ^a  

^a SAMSUNG Electronics   (South Korea)

^b Seoul National University   (South Korea)

Author keywords

Clock; Multiphase; SRAM; Synchronous mirror delay

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ERRORS; INTEGRATED CIRCUIT MANUFACTURE; JITTER; STATIC RANDOM ACCESS STORAGE; SYNCHRONIZATION;

ELECTRON BEAM PROBING; MULTIPHASE LOCKING; PHASE DIFFERENCE; SOFTWARE PACKAGE HSPICE; SYNCHRONIZING ERROR; SYNCHRONOUS MIRROR DELAY; TEST ELEMENTS GROUP;

TIMING CIRCUITS;

EID: 0742286334     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.820871     Document Type: Article

References (12)

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