Analog synchronous mirror delay for high-speed DRAM application

IEEE Journal of Solid-State Circuits

Volumn 34, Issue 4, 1999, Pages 484-493

  Shim, Daeyun ^a   Lee, Dong Yun ^b   Jung, Sanghun ^a   Kim, Chang Hyun ^b   Kim, Wonchan ^a  

^a Seoul National University   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPARATOR CIRCUITS; DYNAMIC RANDOM ACCESS STORAGE; PHASE LOCKED LOOPS; PULSE GENERATORS; SYNCHRONIZATION; TIMING CIRCUITS;

ANALOG SYNCHRONOUS MIRROR DELAY (ASMD); CHARGE PUMPS; CLOCK SYNCHRONIZATION;

DELAY CIRCUITS;

EID: 0033114932     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.753681     Document Type: Article

References (3)

1. T. Saeki, Y. Nakaoka, M. Fujita, A. Tanaka, K. Nagata, K. Sakakibara, T. Matano, Y. Hosino, K. Miyano, S. Isa, S. Nakazawa, E. Kakehashi, J. M. Drynan, M. Komuro, T. Fukase, H. Iwasaki, M. Takenaka, J. Sekine, M. Igeta, N. Nakanishi, T. Itani, K. Yoshida, H. Yoshino, S. Hashimoto, T. Yoshii, M. Ichinose, T. Imura, M. Uziie, S. Kikuchi, K. Koyama, Y. Fukuzo, and T. Okubo, "A 2.5-ns clock access, 250 MHz, 256-Mb SDRAM with synchronous mirror delay," IEEE J. Solid-State Circuits, vol. 31, pp. 1656-1665, Nov. 1996.
2. J.-M. Han, J.-B. Lee, S.-S. Yoon, S.-J. Jeong, C. Park, I.-J. Cho, S.-H. Lee, and D.-I. Seo, "Skew minimization technique for 256 M-bit synchronous DRAM and beyond," in Proc. Symp. VLSI Circuits, June 1996, pp. 192-103.
3. T. Saeki, H. Nakamura, and J. Shimmizu, "A 10 ps jitter 2 clock cycle lock time CMOS clock generator based on an interleaved synchronous mirror delay scheme," in Proc. Symp. VLSI Circuits, June 1997, pp. 109-110.