Automatic VHDL restructuring for RTL synthesis optimization and testability improvement

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1998, Pages 436-441

  Corvino, Dario ^a   Epicoco, Italo ^a   Ferrandi, Fabrizio ^a   Fummi, Franco ^a   Sciuto, Donatella ^a  

^a POLITECNICO DI MILANO   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; CRITICAL PATH ANALYSIS; DATA PROCESSING; DESIGN FOR TESTABILITY; FINITE AUTOMATA; OPTIMIZATION; SEQUENTIAL SWITCHING;

DATA PATH; REGISTER TRANSFER LEVEL; VHDL;

COMPUTER HARDWARE DESCRIPTION LANGUAGES;

EID: 0032298275     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)