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Volumn , Issue , 2003, Pages 219-222

InP HBT integrated circuit technology with selectively implanted subcollector and regrown device layers

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CURRENT DENSITY; ELECTRIC RESISTANCE; GATES (TRANSISTOR); HETEROJUNCTION BIPOLAR TRANSISTORS; MOLECULAR BEAM EPITAXY; OSCILLATORS (ELECTRONIC); SECONDARY ION MASS SPECTROMETRY; SEMICONDUCTING INDIUM PHOSPHIDE; SEMICONDUCTOR DEVICE STRUCTURES;

EID: 0348195866     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/gaas.2003.1252398     Document Type: Conference Paper
Times cited : (9)

References (8)
  • 7
  • 8
    • 0035395944 scopus 로고    scopus 로고
    • Demonstration of sub-5 ps CML ring oscillator gate delay with reduced parasitic AlInAs/InGaAs HBT
    • July
    • M. Sokolich, A.R. Kramer, Y. K. Boegeman, R.R. Martinez, "Demonstration of sub-5 ps CML ring oscillator gate delay with reduced parasitic AlInAs/InGaAs HBT", IEEE Electron Device Lett., Vol. EDL-22, pp. 309-311, July 2001.
    • (2001) IEEE Electron Device Lett. , vol.EDL-22 , pp. 309-311
    • Sokolich, M.1    Kramer, A.R.2    Boegeman, Y.K.3    Martinez, R.R.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.