Equivalent waveform propagation for static timing analysis

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2003, Pages 169-175

  Hashimoto, Masanori ^a   Yamada, Yuji ^a   Onodera, Hidetoshi ^a  

^a KYOTO UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COSTS; STATIC TIMING ANALYSIS (STA);

CAPACITANCE; COMPUTATIONAL METHODS; CROSSTALK; DELAY CIRCUITS; GATES (TRANSISTOR); INTERCONNECTION NETWORKS; SPURIOUS SIGNAL NOISE; TRANSFER FUNCTIONS; VOLTAGE CONTROL; WAVEFORM ANALYSIS;

CMOS INTEGRATED CIRCUITS;

EID: 0348040165     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)

1. A. Odabasioglu, M. Celik and L. T. Pileggi, "PRIMA: Passive reduced-order interconnect macromodeling algorithm," Proc. ICCAD, pp.58-65, 1991.
2. N. H. E. Weste, K. Eshraghian, "Principles of CMOS VLSI Design, 2nd edition," Addison-Wesley Publishing Company, 1992.
3. F. Dartu, N. M. Menezes and L. T. Pileggi, "Performance computation for precharacterized CMOS gates with RC-loads," IEEE Trans. CAD, pp.544-553, 1996.
4. M. Hashimoto, Y. Yamada and H. Onodera, "Capturing Crosstalk-Induced Waveform for Accurate Static Timing Analysis," Proc. ISPD, pp. 18-23, 2003.
5. R. B. Hitchcock, G. L. Smith and D. D. Cheng, "Timing Analysis of Computer Hardware," IBM Journal of Research and Development, Vol. 26, No. 1, pp.100-105, January 1982.
6. K. Agarwal, Y. Cao, T. Sato, D. Sylvester and C. Hu, "Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis," Proc. ASP-DAC, pp.77-84, 2002.
7. Semiconductor Industry Association, International Technology Roadmap for Semiconductors, 2001.
8. S. Sirichotiyakul, D. Blaauw, C. Oh, R. Levy, V. Zolotov and J. Zuo, "Driver Modeling and Alignment for Worst-Case Delay Noise," Proc. DAC, pp.720-725, 2001.
9. Y. Sasaki and G. D. Micheli, "Crosstalk Delay Analysis using Relative Window Method," Proc. ASIC/SOC Conference, pp.9-13, 1999.
10. J. Cong, D. Z. Pan, and P. V. Srinivas, "Improved Crosstalk Modeling for Noise Constrained Interconnect Optimization," Proc. ASP-DAC, pp.373-378, 2001.
11. F. Chang, C. Chen and Prasad Subramaniam, "An Accurate and Efficient Gate Level Delay Calculator for MOS Circuits," Proc. DAC, pp.282-287, 1988.
12. P. R. O'Brien and T. L. Savarino, "Modeling the Driving-Point Characteristic of Resistive Interconnect for Accurate Delay Estimation," Proc. ICCAD, pp. 19-25, 1992.
13. C. Cheng, J. Lillis, S. Lin and N. H. Chang, "Interconnect Analysis and Synthesis," A Wiley Interscience Publication, 2000.
14. X. Yang, C. -K. Cheng, W. H. Ku and R. J. Carragher, "Hurwitz Stable Reduced Order Modeling for RLC Interconnect Trees," Proc. ICCAD, pp.222-228, 2000.