Estimating potential parallelism for platform retargeting

Proceedings - Working Conference on Reverse Engineering, WCRE

Volumn 2002-January, Issue , 2002, Pages 55-64

  Wills, Linda ^a   Taha, Tarek ^a   Baumstark, Lewis ^a   Wills, Scott ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Computer applications; Concurrent computing; Consumer products; Embedded computing; Explosions; Multimedia computing; Parallel algorithms; Parallel processing; Process design; Reverse engineering

Indexed keywords

BENCHMARKING; COMPUTER APPLICATIONS; CONSUMER PRODUCTS; EXPLOSIONS; MECHANISMS; PARALLEL ALGORITHMS; PROCESS DESIGN; PRODUCT DESIGN; REVERSE ENGINEERING;

CONCURRENT COMPUTING; DYNAMIC ANALYSIS TECHNIQUES; EMBEDDED COMPUTING; INHERENT PARALLELISM; MULTIMEDIA APPLICATIONS; MULTIMEDIA COMPUTING; PARALLEL PROCESSING; PROCESSOR PERFORMANCE;

PARALLEL PROCESSING SYSTEMS;

EID: 0347151294     PISSN: 10951350     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/WCRE.2002.1173064     Document Type: Conference Paper

References (18)

1. D.W. Wall, "Limits of Instruction-level Parallelism," in Proc. ASPLOS-IV, Santa Clara, CA, pp. 176-188, Apr. 1991.
2. A. Peleg and U. Weiser, "MMX Technology Extension to the Intel Architecture," in IEEE Micro, vol. 16, no. 4, pp. 51-59, Aug. 1996.
3. D. M. Tullsen, S. J. Eggers, H. M. Levy, "Simultaneous Multithreading: Maximizing on-chip parallelism," in Int. Symp. on Computer Architectures (ISCA-22), 1995.
4. S. Eggers, J. Emer, H. Levy, J. Lo, R. Stamm, and D. Tullsen, "Simultaneous Multithreading: A Platform for Next-Generation Processors," IEEE Micro, Vol. 17, No. 5, pp. 12-19, Sept/Oct. 1997.
5. L. Hammond, B. A. Nayfeh, and K. Olukotun, "A SingleChip Multiprocessor", IEEE Computer, 30:(9), September 1997, pp. 70-85.
6. th Working Conference on Reverse Engineering (WCRE-98), pp. 2-9, Honolulu, HI, Oct. 1998.
7. Spec CINT95 and CFP95 Benchmarks, Open Systems Group, online at http://www.specbench.org/osg/.
8. C. Lee, M. Potkonjak, and W. Mangione-Smith, "MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications Systems," MICRO-30, www.icsl.ucla.edu/~billms/Publications/mediabench.pdf, 1997.
9. L. Codrescu, "ATLAS: A Dynamically Parallelizing Chip-Multiprocessor for Gigascale Integration," Georgia Institute of Technology, Ph.D. Thesis, April 2000. Available at http://www.ece.gatech.edu/~scotty/codrescu-thesis.pdf.
10. M. Tremblay, et. al, "VIS Speeds New Media Processing," IEEE Micro, 16:(4), pp. 10-20, Aug. 1996.
11. M. Phillip, et al. AltiVec Tecnology; Accelerating Media Processing Across the Spectrum," HOTCHIPS, Aug. 1998.
12. S. Oberman, et al. AMD 3DNow! Technology and the K6-2 Microprocessor, in HOTCHIPS10, Aug. 1998.
13. R. Lee and M. Smith, Media Processing: A New Design Target, IEEE Micro, Vol. 16, No. 4, pp. 6-9, August 1996.
14. D. Burger and T. A. Austin. The SimpleScalar tool set, version 2.0. Technical Report #1342. University of Wisconsin-Madison Computer Science, June 1997.
15. A. Nicolau and J. Fisher, "Measuring the Parallelism Available for Very Long Instruction Word Architectures," IEEE Trans. on Computers, 33:(11), Nov. 1984, pp. 968-976.
16. G. S. Tjaden and M.J. Flynn, "Detection and parallel execution of independent instructions," IEEE Trans. on Computers, vol. C-19, pp. 889-895, Oct. 1970.
17. th Int. Symp. on Computer Architecture (ISCA-19), pp. 46-57, 1992.
18. J. T. Oplinger, D. L. Heine, and M. S. Lam, "In Search of Speculative Thread-Level Parallelism," in Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, Newport Beach, CA, Oct. 1999.