Bus architecture synthesis for hardware-software co-design of deep submicron systems on chip

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2003, Pages 126-133

  Thepayasuwan, Nattawut ^a   Damle, Vaishali ^a   Doboli, Alex ^a  

^a STONY BROOK UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER AIDED DESIGN; DESIGN FOR TESTABILITY; ELECTRIC NETWORK TOPOLOGY; EMBEDDED SYSTEMS; MICROPROCESSOR CHIPS;

BUS ARCHITECTURE SYNTHESIS; DEEP SUBMICRON SYSTEMS ON CHIP;

INTEGRATED CIRCUIT LAYOUT;

EID: 0345413297     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (22)

1. "DesignWare AMBA On-Chip Bus Solution", www.convergencepromotions.com/ARM/catalog/156.html.
2. IBM Blue Logic Technology, //http:www-3.ibm.com/chips/bluelogic/.
3. IBM CoreConnect Bus Architecture White Paper, //http:www-3.ibm.com/chips/products/coreconnect/index.html.
4. SRC Research needs in Logic and Physical Level Design and Analysis, August 202.
5. T. R. Bednar, P. H. Buffet, R. J. Darden, S. W. Gould, P. S. Zuchowski, "Issues and Strategies for the Physical Design of System-on-Chip ASICs", IBM J. of Research & Development, Vol. 46, No. 6, Nov. 2002, pp. 661-673.
6. R. Bergamaschi, W. Lee, "Designing Systems-on-Chip using Cores", Proc. of the DAC, 2000, pp. 420-425.
7. J. Darringer, R. Bergamaschi, S. Battacharyya, D. Brand, A. Herkersdorf, J. Morell, I. Nair, P. Sagmeister, Y. Shin, "Early Analysis Tools for System-on-a-Chip Design", IBM J. of Research & Development, Vol. 46, No. 6, 2002, pp. 691-707.
8. J. M. Daveau, G. G. Marchioro, T. Ben Ismail, A. A. Jerraya, "Protocol Selection and Interface Generation for HW-SW Codesign", IEEE Trans. on VLSI Systems, Vol. 5, No. 1, pp. 136-144, March 1997.
9. R. P. Dick, N. K. Jha, "MOCSYN: Multiobjective core-based single-chip system synthesis," Design Automation and Test in Europe Conf., pp.263-270, 1999.
10. A. Doboli, "Integrated Hardware/Software Co-synthesis and High Level Synthesis for Design of Embedded Systems under Power and Latency Constraints", Proc. of Design, Automation and Test in Europe Conference, 2001.
11. M. Drinic, D.Kirovski, S. Meguerdichian, M. Potkonjak, "Latency-Guided On-Chip Bus Network Design", Proc. of the ICCAD, 2000, pp. 420-423.
12. D. Gajski, F. Vahid, "Specification and Design of Embedded Hardware/Software Systems", IEEE Design & Test of Computers, Spring 1995, pp. 53-67.
13. M.Gasteier, M. Glesner, "Bus-Based Communication Synthesis on System Level", ACM Transactions on DAES, Vol. 4, No. 1, January 1999, pp. 1-11.
14. J. Hu, Y. Deng, R. Marculescu, "System-level Point-to-Point Communication Synthesis Using Floorplanning Information", Proc. of the International Conference on VLSI Design, 2002.
15. K. Lahiri, A.Raghunathan, S. Dey, "Efficient Exploration of the SoC Communication Architecture Design Space", Proc. of the ICCAD, 2000, pp. 424-430.
16. S. Meguerdician, M. Drinic, D. Kirovski, "Latency-Driven Design of Multi-Purpose Systems-on-Chip", Proc. of the DAC, 2001.
17. R. Ortega, G. Boriello, "Communication Synthesis for Distributed Embedded Systems", Proc. of the ICCAD, 1998, pp. 437-444.
18. C.Reeves et al. "Modern Heuristic Techniques for Combinatorial Problems", J. Wiley, 1993.
19. T. Seceleanu et al., "On-Chip Segmented Bus: A Self-Timed Approach", Proc. of the IEEE ASIC/SOC Conference, pp. 216-220.
20. N. Sherwani, "Algorithms for VLSI Physical Design Automation", Kluwer, 1999.
21. D. Sylvester, K. Keutzer, "A Global Wiring Paradigm for Deep Submicron Design", IEEE Trans. on CADICS, Vol. 19, No. 2, pp. 242-252, February 2000.
22. T. Y. Yen, W. Wolf, "Communication Synthesis for Distributed Systems", Proc. of the ICCAD, 1995.