Phase-Noise Cancellation Design Tradeoffs in Delta-Sigma Fractional-N PLLs

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 50, Issue 11, 2003, Pages 829-838

  Pamarti, Sudhakar ^a   Galton, Ian ^b  

^a RAMBUS INC   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Delta sigma modulator; Fractional N PLL; Phased locked loop (PLL); Segmented digital to analog converter (DAC); Synthesizer

Indexed keywords

BANDWIDTH; DELTA SIGMA MODULATION; DIGITAL TO ANALOG CONVERSION; ELECTRIC CURRENTS; ERROR ANALYSIS; MODULATORS; SPURIOUS SIGNAL NOISE;

PHASE NOISE CANCELLATION;

PHASE LOCKED LOOPS;

EID: 0344943240     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSII.2003.819117     Document Type: Article

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