Symbolic failure analysis of custom circuits due to excessive leakage current

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2003, Pages 70-75

  Song, H Y ^a   Bohidar, S ^a   Bahar, R Iris ^a   Grodstein, Joel ^b  

^a BROWN UNIVERSITY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGEBRA; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; FAILURE ANALYSIS; LEAKAGE CURRENTS; SPURIOUS SIGNAL NOISE;

ALGEBRAIC DECISION DIAGRAMS; CHANNEL CONNECTED REGION;

INTEGRATED CIRCUIT LAYOUT;

EID: 0344551129     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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