Charge-recycling voltage domains for energy-efficient low-voltage operation of digital CMOS circuits

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2003, Pages 98-102

  Rajapandian, Saravanan ^a   Xu, Zheng ^a   Shepard, K L ^a  

^a Department of Earth and Environmental Sciences   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POWER SUPPLIES TO APPARATUS; ENERGY EFFICIENCY; INTEGRATED CIRCUIT LAYOUT; VOLTAGE CONTROL;

CHARGE RECYCLING VOLTAGE; DYNAMIC VOLTAGE SCALING;

DIGITAL INTEGRATED CIRCUITS;

EID: 0344551122     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. G. Qu and et al. Energy minimization of system pipelines using multiple voltages. In Proc. IEEE International Symposium on Circuits and Systems, 1999.
2. G. Semeraro, G. Magklis, R. Balasurbramonian, D. H. Albonesi, S. Dwaradasas, and M. L. Scott. Energy-efficient processor design using multiple clock domains with dynamic voltage and frequency scaling. In Proc. Intl. Symp. on High Performance Computer Architecture, 2002.
3. T. D. Burd and R. W. Broderson. Design issues for dynamic voltage scaling. In Intl. Symp. on Low Power Electronics and Design, 2000.
4. K. Usami and M. Horowitz. Clustered voltage scaling technique for low-power design. In Proc. Workshop on Low Power Design, 1995.
5. D. E. Lackey, P. S. Zuchowski, T. R. Bednar, D. W. Stout, S. W. Gould, and J. M. Cohn. Managing power and performance for system-on-chip designs using voltage islands. In Proceedings of the IEEE/ACM International Conference on Computer Aided-Design, pages 195-202, 2002.
6. G.-W. Wei and M. Horowitz. A fully digital, energy-efficient adaptive power-supply regulator. IEEE Journal Solid-State Circuits, pages 520-528, April 2000.
7. H. Yamauchi, H. Akamatsu, and T. Fujita. An asymptotically zero power charge-recycling bus architecture for battery-operated ultrahigh data rate ULSI's. IEEE Journal Solid-State Circuits, pages 423 - 431, April 1995.
8. Byung-Do Yang and Lee-Sup Kim. A low-power ROM using charge recycling and charge sharing techniques. IEEE Journal Solid-State Circuits, 38:641 - 653, April 2003.
9. J. T. Kao and A. P. Chandrakasan. Dual-threshold voltage techniques for low-power digital circuits. IEEE Journal Solid-State Circuits, pages 1009 - 1018, July 2000.
10. J. Montanaro and et al. A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor. IEEE Journal Solid-State Circuits, 31:1703-1712, November 1996.