Determination of film and surface recombination in thin-film SOI devices using gated-diode technique

Solid-State Electronics

Volumn 48, Issue 3, 2004, Pages 389-399

  Rudenko, T ^a   Rudenko, A ^a   Kilchytska, V ^a   Cristoloveanu, S ^b   Ernst, T ^b,c   Colinge, J P ^d   Dessard, V ^e   Flandre, D ^e  

^a INSTITUTE OF SEMICONDUCTOR PHYSICS   (Ukraine)

^b IMEP LAHC   (France)

^c CEA LETI   (France)

^d University of California   (United States)

^e UNIVERSITÉ CATHOLIQUE DE LOUVAIN   (Belgium)

Author keywords

Carrier recombination lifetime; Fully depleted SOI MOS device; SIMOX; Surface recombination velocity; UNIBOND; ZMR

Indexed keywords

BIPOLAR TRANSISTORS; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; MOS DEVICES;

GATED-DIODE TECHNIQUE; SURFACE RECOMBINATION VELOCITY;

THIN FILMS;

EID: 0344035502     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2003.09.004     Document Type: Article

References (15)

1. Colinge J.-P. Silicon-on-insulator technology: materials to VLSI. 2nd ed. 1997;Kluwer, Norwell, MA.
2. Kato K., Wada T., Taniguchi K. Analysis of kink characteristics in silicon-on-insulator MOSFET's using two-carrier modeling. IEEE Trans. Electron Dev. 32(2):1985;458-462.
3. Wei A., Sherony M.J., Antoniadis D.A. Effect of floating body charge in SOI MOSFET design. IEEE Trans. Electron Dev. 45(2):1988;430-438.
4. Cristoloveanu S., Li S.S. Electrical characterization of silicon-on-insulator materials and devices. 1995;Kluwer, Norwell, MA.
5. Munteanu D., Weiser D.A., Cristoloveanu S., Faynot O., Pelloie J.L., Fossum J.G. Generation/recombination transient effects in SOI transistors: systematic experiment and simulations. IEEE Trans. Electron Dev. 45(8):1998;1678-1683.
6. Colinge J.-P. Reduction of floating substrate effect in thin-film SOI MOSFETs. Electron. Lett. 22(4):1986;187-188.
7. Colinge J.-P. Reduction of kink effect in thin-film SOI MOSFET's. IEEE Electron Dev. Lett. 9(2):1988;97-99.
8. Sturm J.C., Tokunaga K., Colinge J.-P. Increased drain saturation current in ultra-thin silicon-on-insulator (SOI) MOS transistors. IEEE Electron Dev. Lett. 9(9):1988;460-463.
9. Flandre D., Ferreira L., Jespers P.G.A., Colinge J.-P. Modeling and application of fully-depleted SOI MOSFETs for low-voltage low-power analogue CMOS circuits. Solid-State Electron. 39(4):1996;455-460.
10. Flandre D., et al. Fully-depleted SOI CMOS technology for low-voltage low-power mixed digital/analog/microwave circuits. Analog Integr. Circ. Signal Process. 21:1999;213-228.
11. Rudenko T.E., Rudenko A.N., Lysenko V.S. Electrical properties of ZMR SOI structures: characterization techniques and experimental results. Physical and technical problems of SOI structures and devices. 1995;169-179 Kluwer, Norwell, MA.
12. Ernst T., Cristoloveanu S., Vandooren A., Rudenko T., Colinge J.-P. Recombination current modeling and carrier lifetime extraction in dual-gate fully-depleted SOI devices. IEEE Trans. Electron Dev. 46(7):1999;1503-1509.
13. 2 interface. IEEE Trans. Electron Dev. 48(4):2001;685-687.
14. © process Microelectron. Eng. 36(1-4):1997;233-240.
15. Givargizov E.I., Loukin V.A., Limanov A.B. Defect engineering in SOI films prepared by zone-melting recrystallization technique. Physical and technical problems of SOI structures and devices. 1995;27-38 Kluwer, Norwell, MA.