A high-speed and low-voltage associative co-processor with hamming distance ordering using word-parallel and hierarchical search architecture

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2003, Pages 643-646

  Oike, Yusuke ^a   Ikeda, Makoto ^a   Asada, Kunihiro ^a  

^a UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DATA COMPRESSION; MICROPROCESSOR CHIPS; PATTERN RECOGNITION;

CONTEXT ADDRESSABLE MEMORIES; DEEP SUB-MICRON PROCESS; HAMMING DISTANCE; HIERARCHICAL SEARCH ARCHITECTURE; SEARCH SIGNAL;

COMPUTER ARCHITECTURE;

EID: 0242696030     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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