Minimum-distance search circuit using dual-line PWM signal processing and charge-packet counting techniques

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 40, Issue , 1997, Pages 42-43

  Nagata, Makoto ^a   Yoneda, Takahiro ^a   Nomasaki, Daisuke ^a   Sano, Makoto ^a   Iwata, Atsushi ^a  

^a HIROSHIMA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; BINARY SEQUENCES; CMOS INTEGRATED CIRCUITS; DIGITAL SIGNAL PROCESSING; FLIP FLOP CIRCUITS; MICROPROCESSOR CHIPS; MOS DEVICES; PACKET SWITCHING; PULSE WIDTH MODULATION; SHIFT REGISTERS; TIME DOMAIN ANALYSIS;

CHARGE PACKET COUNTING TECHNIQUES; CMOS MINIMUM DISTANCE SEARCH CIRCUIT (MDS); DUAL LINE PULSE WIDTH MODULATION; WINNER TAKE ALL (WTA) CIRCUITS;

IMAGE PROCESSING;

EID: 0031069029     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (1)