An architecture for compact associative memories with deca-ns nearest-match capability up to large distances

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 443, Issue , 2001, Pages 170-171

  Mattausch, Hans Jürgen ^a   Gyohten, Takayuki ^a   Soda, Yoshihiro ^a   Koide, Tetsushi ^b  

^a HIROSHIMA UNIVERSITY   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFICATION; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; DATA COMPRESSION; MOSFET DEVICES; PATTERN RECOGNITION; STATIC RANDOM ACCESS STORAGE;

BIT COMPARISON (BC); WORD COMPARISON (WC);

ASSOCIATIVE STORAGE;

EID: 0035054906     PISSN: 01936530     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISSCC.2001.912590     Document Type: Article

References (7)

1. Analog electronic neural network circuits
2. A fully parallel vector-quantization processor for real-time motion-picture compression
3. Associative IC memories with relational search and nearest-match capabilities
4. Time-domain minimum-distance detector and its application to low-power coding scheme on chip-interface
5. Winner-take-all networks of O(N) complexity