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Volumn , Issue CIRCUITS SYMP., 2002, Pages 252-255

Fully-parallel pattern-matching engine with dynamic adaptability to Hamming or Manhattan distance

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DATA COMPRESSION; DATA STORAGE EQUIPMENT; PATTERN MATCHING; REAL TIME SYSTEMS;

EID: 0242443354     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (24)

References (7)
  • 1
    • 0003592184 scopus 로고    scopus 로고
    • The pattern recognition basis of artificial intelligence
    • Los Alamitos, CA: IEEE Computer Society
    • D. R. Tveter "The Pattern Recognition Basis of Artificial Intelligence", Los Alamitos, CA: IEEE Computer Society, 1998.
    • (1998)
    • Tveter, D.R.1
  • 2
    • 0003959189 scopus 로고
    • Vector quantization and signal compression
    • Boston, MA: Kluwer Academic
    • A. Gersho and R. M. Gray, "Vector Quantization and Signal Compression", Boston, MA: Kluwer Academic, 1992.
    • (1992)
    • Gersho, A.1    Gray, R.M.2
  • 3
    • 0033363024 scopus 로고    scopus 로고
    • A low-power and high-performance CMOS fingerprint sensing and encoding architecture
    • S. Jung et al., "A Low-Power and High-Performance CMOS Fingerprint Sensing and Encoding Architecture", IEEE J. Solid-State Circuits, vol. 34, pp. 978-984, 1999.
    • (1999) IEEE J. Solid-State Circuits , vol.34 , pp. 978-984
    • Jung, S.1
  • 4
    • 0033280274 scopus 로고    scopus 로고
    • A single-chip fingerprint sensor and identifier
    • S. Shigematsu et al., "A Single-Chip Fingerprint Sensor and Identifier", IEEE J. Solid-State Circuits, vol. 34, pp. 1852-1859, 1999.
    • (1999) IEEE J. Solid-State Circuits , vol.34 , pp. 1852-1859
    • Shigematsu, S.1
  • 5
    • 0034318168 scopus 로고    scopus 로고
    • A parallel vector-quantization processor eliminating redundant calculations for real-time motion picture compression
    • T. Nozawa et al., "A Parallel Vector-Quantization Processor Eliminating Redundant Calculations for Real-Time Motion Picture Compression", IEEE J. Solid-State Circuits, vol. 35, pp. 1744-1751, 2000.
    • (2000) IEEE J. Solid-State Circuits , vol.35 , pp. 1744-1751
    • Nozawa, T.1
  • 6
    • 0035054906 scopus 로고    scopus 로고
    • An architecture for compact associative memories with deca-ns nearest-match capability up to large distances
    • H. J. Mattausch et al., "An Architecture for Compact Associative Memories with Deca-ns Nearest-Match Capability up to Large Distances", IEEE ISSCC Dig. of Tech. Papers, pp. 170-171, 2001.
    • (2001) IEEE ISSCC Dig. of Tech. Papers , pp. 170-171
    • Mattausch, H.J.1
  • 7
    • 0031674052 scopus 로고    scopus 로고
    • Rail-to-rail multiple-input min/max circuit
    • I. E. Opris, "Rail-to-Rail Multiple-Input Min/Max Circuit", IEEE Trans. Circuits and Systems II, vol. 45, 137-141, 1998.
    • (1998) IEEE Trans. Circuits and Systems II , vol.45 , pp. 137-141
    • Opris, I.E.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.