A 125MHz burst mode 0.18μm 128Mbit 2 bits per cell flash memory

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue CIRCUITS SYMP., 2002, Pages 304-307

  Castro, H A ^a   Augustine, K ^a   Balasubrahmanyam, S ^a   Bressie, T J ^a   Chandramouli, S ^a   Christensen, G V ^a   Dayley, M G ^a   Elmhurst, D R ^a   Fan, K ^a   Goldman, M ^a   Haid, C ^a   Haque, R ^a   Ishac, M I ^a   Khandaker, M M ^a   Kreifels, J A ^a   Li, B ^a   Loe, K D ^a   Ly, T H ^a   Marvin, F C ^a   Melcher, R L ^a   Monasa, S P ^a   Nambiar, R R ^a   Ngo, Q H ^a   Padilla Jr , R ^a   Pathak, B M ^a   Rahman, A ^a   Rajagopal, R ^a   Ramamurthi, K ^a   Saini, S S ^a   Sayed, A T ^a   Sharif, I ^a   Srinivasan, B ^a   Szwarc, M ^a   Vadlamudi, G ^a   Viajedor, V ^a   Zeng, R W ^a   more..

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); CELLULAR ARRAYS; ELECTRIC POWER SUPPLIES TO APPARATUS; LOGIC DESIGN; MICROPROCESSOR CHIPS; SHIFT REGISTERS; THRESHOLD VOLTAGE;

CELL FLASH MEMORY; SENSE AMPLIFIER;

FLASH MEMORY;

EID: 0242611609     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. tm Flash Memory Technology," IEEE IEDM Tech. Digest 403, pp 267-268, Dec 1999
2. Bauer, M. et al., "A Multilevel-cell 32 Mb Flash Memory". Solid State Circuits Conference, 1995. Digest of Technical Papers, pp 132-133, 351, 41st ISSCC, 1995
3. Pathak, B. et al., "A 1.8v 100MHz Flexible Read While Write Flash Memory" ISSCC Digest of Technical Papers, Feb 2001.