Partially-depleted SOI compact model - formulation and parameter extraction

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2000, Pages 206-207

  Fung, S K H ^a   Wagner, L ^a   Sherony, M ^a   Zamdmer, N ^a   Sleight, J ^a   Michel, M ^a   Leobandung, E ^a   Lo, S H ^a   Chen, T C ^a   Assaderaghi, F ^a  

^a IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; MICROPROCESSOR CHIPS; SEMICONDUCTOR DEVICE MODELS; VLSI CIRCUITS;

PARTIALLY DEPLETED SILICON ON INSULATOR (PDSOI) TECHNOLOGY;

SILICON ON INSULATOR TECHNOLOGY;

EID: 0033682246     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)