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Volumn , Issue , 1996, Pages 471-476
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Module compaction in FPGA-based regular datapaths
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Author keywords
[No Author keywords available]
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Indexed keywords
COMPUTER ARCHITECTURE;
CRITICAL PATH ANALYSIS;
DELAY CIRCUITS;
ELECTRIC NETWORK SYNTHESIS;
INTEGRATED CIRCUIT LAYOUT;
LOGIC DESIGN;
MULTICHIP MODULES;
OPTIMIZATION;
PARALLEL PROCESSING SYSTEMS;
VLSI CIRCUITS;
FIELD PROGRAMMABLE GATE ARRAYS (FPGAS);
LOCAL LOGIC SYNTHESIS;
REGULAR DATAPATHS;
LOGIC GATES;
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EID: 0029695758
PISSN: 0738100X
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1145/240518.240608 Document Type: Conference Paper |
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Times cited : (7)
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References (19)
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