Performance assessment of scaled strained-Si channel-on-insulator (SSOI) CMOS

Solid-State Electronics

Volumn 48, Issue 2, 2004, Pages 239-243

  Kim, Keunwoo ^a   Chuang, Ching Te ^a   Rim, Kern ^a   Joshi, Rajiv V ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

Band offsets; Floating body effects; SOI; SSOI; Strained Si MOSFETs

Indexed keywords

CAPACITANCE; CARRIER MOBILITY; MOSFET DEVICES; SILICON; STRAIN;

FLOATING-BODY EFFECTS;

CMOS INTEGRATED CIRCUITS;

EID: 0242271886     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0038-1101(03)00296-X     Document Type: Article

References (9)

1. Rim K et al. Strained Si NMOSFETs for high performance CMOS technology. In: Symp VLSI Tech, June 2001. p. 59-60.
2. Fossum, JG. UFSOI/API-6.0 with UFPDB-1.0, University of Florida, 2001. Available from: http://www.soi.tec.ufl.edu.
3. Mizuno T et al. High performance CMOS operation of strained-SOI MOSFETs using thin film SiGe-on-insulator substrate. In: Symp VLSI Tech, June 2002. p. 106-7.
4. Taur Y., Ning T.H. Fundamentals of modern VLSI devices. 1998;Cambridge University Press, New York.
5. Rim K et al. Characterization and device design of Sub-100 nm strained Si N- and PMOSFETs. In: Symp VLSI Tech, June 2002. p. 98-9.
6. Mizuno T.et al. High performance strained-Si p-MOSFETs on SiGe-on-insulator substrates fabricated by SIMOX technology. IEDM Tech. Dig. 1999;934-936.
7. Huang L-J et al. Carrier mobility enhancement in strained Si-on-insulator fabricated by wafer boding. In: Symp VLSI Tech, 2001. p. 57-8.
8. x source structure. IEEE Trans. Electron. Dev. (Mar.):1997;423-430.
9. Pelella M., Fossum J.G. On the performance advantage of PD/SOI CMOS with floating bodies. IEEE Trans. Electron. Dev. (Jan.):2002;96-104.