Test generation for crosstalk effects in VLSI circuits

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 1996, Pages 628-631

  Lee, Kyung Tek ^a   Nordquist, Clay ^a   Abraham, Jacob A ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CAPACITANCE; CROSSTALK; DIELECTRIC MATERIALS; ELECTRIC CURRENTS; GEOMETRY; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; RESISTORS; SIGNAL PROCESSING; TRANSMISSION LINE THEORY; VECTORS;

AUTOMATIC TEST EXTRACTOR FOR GLITCH; CLOCK TRANSITION TIME; CROSSTALK DELAY; CROSSTALK EFFECTS; CROSSTALK GLITCH; INTERCONNECT LINES;

VLSI CIRCUITS;

EID: 0029699584     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)