A new technology mapping for CPLD under the time constraint

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2001-January, Issue , 2001, Pages 235-238

  Kim, Jae Jin ^a   Kim, Hi Seok ^a   Lin, Chi Ho ^b  

^a Chongju University   (South Korea)

^b Semyung University   (South Korea)

Author keywords

Circuit synthesis; Clustering algorithms; Combinational circuits; Computer science; Digital circuits; Educational technology; Equations; Field programmable gate arrays; Logic functions; Time factors

Indexed keywords

ALGORITHMS; BOOLEAN ALGEBRA; COMBINATORIAL CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER SCIENCE; CONFORMAL MAPPING; DIGITAL CIRCUITS; EDUCATIONAL TECHNOLOGY; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTEGRATED CIRCUITS; LOGIC CIRCUITS; LOGIC DEVICES; LOGIC SYNTHESIS; MAPPING;

BOOLEAN EQUATIONS; CIRCUIT SYNTHESIS; EQUATIONS; LOGIC FUNCTIONS; TECHNOLOGY MAPPING; TECHNOLOGY MAPPING ALGORITHMS; TIME CONSTRAINTS; TIME FACTORS;

CLUSTERING ALGORITHMS;

EID: 62349102339     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2001.913311     Document Type: Conference Paper

References (10)

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3. The MACH 4 Family Data Sheet, Advanced Micro Devices, 1996
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5. R.J Francis, J. Rose and Z. Vranestic, "Chortle-crf : Fast Technology Mapping for Lookup Table-Based FPGAs", 28th ACM/IEEE Design Automation Conference, June 1991, pp.227-233.
6. R.J Francis, J. Rose and Z. Vranestic, "Technology Mapping of Lookup Table-Based FPGAs for Performance", 1991 IEEE Conference on Computer Aided Design, pp. 568-571
7. E. M. Sentovice et al., "SIS : A system for sequential Circuit Synthesis", Technical Report UCM/ERL M92/41, Electronics Research Laboratory, Department of Electrical Engineering and Computer Science, University of California, Berkeley, 1992
8. J.L. Kouloheris, "Empirical Study of the Effect of cell Granularity on FPGA Density and Performance", Ph.D. Thesis, Department of Electrical Engineering, Stanford University, 1993.
9. Jason Helge Anderson, Stephen Dean Brown, "Technology Mapping for Large Complex PLDs", Design Automation Conference, 1998, pp. 698-703
10. Hi-Seok. Kim, Jae-Jin. Kim, Chi-Ho. Lin, " An Efficient CPLD Technology Mapping Under Time Constraint", IEEE Conference on Microelectronics, 2000, pp. 265-268.