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Volumn , Issue , 2003, Pages 261-264

High performance SCR's for on-chip ESD protection in high voltage BCD processes

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC POTENTIAL; MODULATION;

EID: 0043016319     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (6)

References (8)
  • 1
    • 0035158795 scopus 로고    scopus 로고
    • Voltage handling capability and termination techniques of silicon power semiconductor devices
    • Charitat, "Voltage Handling Capability and Termination Techniques of Silicon Power Semiconductor Devices, BCTM (2001), p.175-183
    • (2001) BCTM , pp. 175-183
    • Charitat1
  • 2
    • 0036437982 scopus 로고    scopus 로고
    • Comparison of ESD protection capability of lateral BJT, SCR and bi-directional SCR for hi-voltage BiCMOS circuits
    • V. A. Vashchenko, A. Concannon, M. ter Beek, and P. Hopper "Comparison of ESD Protection Capability of lateral BJT, SCR and bi-directional SCR for Hi-Voltage BiCMOS Circuits", in Proc. BCTM, 2002, pp. 181-184.
    • (2002) Proc. BCTM , pp. 181-184
    • Vashchenko, V.A.1    Concannon, A.2    Ter Beek, M.3    Hopper, P.4
  • 3
    • 0037972885 scopus 로고    scopus 로고
    • A device level negative feedback in the emitter line of SCR-structures as a method to realize latch-up free ESD Protection
    • see paper 2C.5
    • A. Concannon, V.A. Vashchenko, M. ter Beek, and P. Hopper, "A device level negative feedback in the emitter line of SCR-structures as a method to realize latch-up free ESD Protection," in Proceed. of IRPS, 2003,(see paper 2C.5)
    • (2003) Proceed. of IRPS
    • Concannon, A.1    Vashchenko, V.A.2    Ter Beek, M.3    Hopper, P.4
  • 4
    • 84948778506 scopus 로고    scopus 로고
    • Technology CAD evaluation of BiCMOS protection structures operation including spatial thermal runaway
    • V. A. Vashchenko, A. Concannon, M. ter Beek, and P. Hopper "Technology CAD Evaluation of BiCMOS Protection Structures Operation Including Spatial Thermal Runaway,"in Proceed. of ESD/EOS Symposium, 2002, pp.101-110.
    • (2002) Proceed. of ESD/EOS Symposium , pp. 101-110
    • Vashchenko, V.A.1    Concannon, A.2    Ter Beek, M.3    Hopper, P.4
  • 5
    • 0029536334 scopus 로고
    • Bipolar SCR ESD protection for high speed submicron Bipolar/BiCMOS frequency integrated circuits
    • J. Z. Chen, A. Amerasekera, T. Vrotos, "Bipolar SCR ESD protection for high speed submicron Bipolar/BiCMOS frequency integrated circuits," in Proceed. IEDM, (1995), pp.337-340
    • (1995) Proceed. IEDM , pp. 337-340
    • Chen, J.Z.1    Amerasekera, A.2    Vrotos, T.3
  • 6
  • 7
    • 0031274651 scopus 로고    scopus 로고
    • Electrical instability and filamentation in ggMOS protection structures
    • V. A. Vashchenko, Y. Martynov, V.F. Sinkevitch, "Electrical instability and filamentation in ggMOS protection structures," Sol-St. Elec. (1997) p.1761.
    • (1997) Sol-St. Elec. , pp. 1761
    • Vashchenko, V.A.1    Martynov, Y.2    Sinkevitch, V.F.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.