Voltage handling capability and termination techniques of silicon power semiconductor devices

Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting

Volumn , Issue , 2001, Pages 175-183

  Charitat, G ^a  

^a LAAS CNRS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

AVALANCHE DIODES; ELECTRIC BREAKDOWN; ELECTRIC FIELD EFFECTS; IONIZATION; MICROELECTRONICS; SEMICONDUCTOR JUNCTIONS;

AVALANCHE BREAKDOWN;

SEMICONDUCTOR DEVICES;

EID: 0035158795     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (33)

1. Ionization rates of electrons and holes in silicon
2. Electron and hole ionization rates in epitaxial silicon at high electric fields
3. Ionization rates of holes and electrons in silicon
4. Measurement of the ionisation rates in diffused silicon p-n junctions
5. Impact-ionization in silicon at large operating temperature
6. Calculation of avalanche breakdowns voltages of silicon p-n junctions
7. Effect of surface fields on the breakdown of planar silicon p-n junctions
8. Surface breakdown in silicon planar diodes equipped with field plate
9. Design considerations for high-voltage overlay annular diodes
10. Deep-depletion breakdown voltage of silicon-dioxide/silicon MOS capacitors
11. Enhancement of breakdown properties of overlay annular diodes by field shaping resistive films
12. Semi-insulating polycristalline-silicon (SIPOS) passivation technology
13. High voltage planar devices using field plate and semi-resistive layers
14. Improving the dynamic avalanche breakdown of high voltage planar devices using semi-resistive field plates
15. Junction termination extension, a new technique for increasing avalanche breakdown voltage and controlling surface electric field in P-N junctions
16. Optimization and surface charge sensitivity of high-voltage blocking structures with shallow junctions
17. Variation of lateral doping as a field terminator for high-voltage power devices
18. Current developments in high-power thyristors
19. High-voltage planar p-n junctions
20. Design methodology and simulation tool for floating ring termination technique
21. The effect of static and dynamic parasitic charge in the termination area of high voltage devices and possible solutions
22. A review of RESURF technology
23. High voltage thin layer devices (RESURF devices)
24. Optimization of RESURF LDMOS transistors: An analytical approach
25. High voltage RESURF LDMOS for smart power integrated circuits
26. A new junction termination technique for power devices: RESURF LDMOS with sipos layers
27. Novel concepts for high voltage junction termination techniques using very deep trenches
28. Simulated performances of semiconductor superjunction devices
29. Ultra-high voltage device termination using 3D RESURF (super-junction) concept - Experimental demonstration at 6.5 kV
30. Silicon nonlinear capacitors