An integratable dual metal gate CMOS process using an ultrathin aluminum nitride buffer layer

IEEE Electron Device Letters

Volumn 24, Issue 5, 2003, Pages 298-300

  Park, Chang Seo ^a   Cho, Byung Jin ^a   Kwong, Dim Lee ^b  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^b The University of Texas at Austin   (United States)

Author keywords

Aluminum nitride; CMOS; Dual metal gates; Workfunction

Indexed keywords

ANNEALING; CMOS INTEGRATED CIRCUITS; DEPOSITION; DIELECTRIC MATERIALS; ELECTRODES; ETCHING; GATES (TRANSISTOR); SILICA; SUBSTRATES; ULTRATHIN FILMS;

DUAL METAL GATE CMOS PROCESS; ULTRATHIN ALUMINUM NITRIDE; WORK FUNCTION;

ALUMINUM NITRIDE;

EID: 0042674259     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2003.812548     Document Type: Article

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