A simulated annealing approach for automatic extraction of device and material parameters of MOS with SiO2/high-K gate stacks

Biennial University/Government/Industry Microelectronics Symposium - Proceedings

Volumn , Issue , 2003, Pages 218-221

  Li, Fei ^a   Mudanai, Sivakumar P ^c   Fan, Yang Yu ^c   Zhao, Wei ^b   Register, Leonard F ^a   Banerjee, Sanjay K ^a  

^a The University of Texas at Austin   (United States)

^b University of Notre Dame   (United States)

^c NONE

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ANNEALING; CAPACITANCE; DIELECTRIC DEVICES; DOPING (ADDITIVES); ELECTRIC POTENTIAL; ELECTRON TUNNELING; GATES (TRANSISTOR); LEAKAGE CURRENTS; POLYSILICON; SILICA;

QUANTUM EFFECTS;

MOS CAPACITORS;

EID: 0042440932     PISSN: 07496877     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. S. Jallepalli, J. Bude, W. -K. Shih, M. R. Pinto, C. M. Maziar, and A. F. Tasch, "Electron and hole quantization and their impact on deep submicron silicon p- and n- MOSFET characteristics," IEEE Trans. Electron Devices, vol. 44, no. 2, February 1997.
2. S. A. Hareland, S. Krishnamurthy, S. Jallepalli, C. -F. Yeap, A. F. Tasch, and C. M. Maziar, "A computationally efficient model for inversion layer quantization effects in deep submicron n-channel MOSFETs," IEEE Trans. Electron Devices, vol. 43, no. 1, January 1996.
3. S. Mudanai, L. F. Register, A. F. Tasch, and S. K. Banerjee, "Understanding the effects of Wave Function Penetration on the Inversion Layer Capacitance of NMOSFETs," IEEE Electron Device Letters, pp. 145-147, Vol. 22, No. 3 March 2001.
4. Y. Ohkura, "Quantum effects in Si n-MOS inversion layer at high substrate concentration," Solid-State Electronics, 33, p.1581, 1990.
5. 2 n-channel MOS capacitor", IEEE Transactions on Electron Devices, vol. 49, no. 11, pp. 1969-1978, 2002.
6. User's Guide for UTQUANT2.3, University of Texas at Austin, 2001.
7. Yang-Yu Fan, Supplement for UTQUANT Gate Current Simulation, University of Texas at Austin, 2002.
8. S. P. Mudanai, F. Li, L. F. Register, and S. K. Banerjee, "Compact gate capacitance model based on first principles" submitted to IEEE Trans. Electron Devices, Jan. 2003.
9. 2 and high-K gate stacks", in FALL 2002 Gate Stack Engineering Working Group Symposium, Austin, TX, 2002, session 15.
10. S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi, "Optimization by simulated annealing", Science, vol. 220, pp.671-680, 1983.
11. P. J. M. van Laarhoven, and E. H. L. Aarts, Simulated annealing: theory and applications. Holland: D. Reidel Publishing Company, 1987, ch. 7.
12. W. H. Press, S. A. Teukolsky, W. T. Vetterling, B. P. Flannery, Numerical recipes in C: the art of scientific computing, Cambridge University Press, 2002, ch. 10.
13. E. H. Nicollian and J. R. Brews, MOS (Metal Oxide Semiconductor) physics and technology, John Wiley & Sons, 1982, ch. 9.