Tiling, block data layout, and memory hierarchy performance

IEEE Transactions on Parallel and Distributed Systems

Volumn 14, Issue 7, 2003, Pages 640-654

  Park, Neungsoo ^a   Hong, Bo ^b   Prasanna, Viktor K ^b  

^a SAMSUNG Electronics   (South Korea)

^b University of Southern California ^*  (United States)

Author keywords

Block data layout; Cache misses; Memory hierarchy; Tiling; TLB misses

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; DATA PROCESSING; HIERARCHICAL SYSTEMS;

BLOCK DATA LAYOUT;

CACHE MEMORY;

EID: 0042235298     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/TPDS.2003.1214317     Document Type: Article

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