Quantifying the Multi-Level Nature of Tiling Interactions

International Journal of Parallel Programming

Volumn 26, Issue 6, 1998, Pages 641-670

  Mitchell, Nicholas ^a   Högstedt, Karin ^b   Carter, Larry ^b   Ferrante, Jeanne ^b  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b NONE

Author keywords

Compiler; Locality; Memory hierarchy; Parallelism; Tiling

Indexed keywords

COMPUTER ARCHITECTURE; COSTS; DATA STORAGE EQUIPMENT; HIERARCHICAL SYSTEMS; OPTIMIZATION; STORAGE ALLOCATION (COMPUTER);

MEMORY HIERARCHY; MULTILEVEL COST FUNCTIONS; PARALLELISM; TILING;

PARALLEL PROCESSING SYSTEMS;

EID: 0032308685     PISSN: 08857458     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1018782528453     Document Type: Article

References (32)

1. Michael E. Wolf and Monica S. Lam, A data locality optimizing algorithm, Progr. Lang. Design Implementation (1991).
2. Steve Carr and Ken Kennedy, Compiler blockability of numerical algorithms, J. Supercomputing, pp. 114-124 (November 1992).
3. Steve Carr, Kathryn S. McKinley, and Chau-Wen Tseng, Compiler optimizations for improving data locality, Sixth Intl. Conf. Archit. Support Progr. Lang. Oper. Syst., San Jose, California, Oct. 1994.
4. Steve Carr and Ken Kennedy, Improving the ratio of memory operations to floatingpoint operations in loops, Trans. Progr. Lang. Syst. 16(6):1768-1810 (November 1994).
5. Corinne Ancourt and François Irigoin, Scanning polyhedra with DO loops, Principles and Practice of Parallel Progr., pp. 39-50 (April 1991).
6. Michael E. Wolf and Monica S. Lam, A loop transformation theory and an algorithm to maximize parallelism, IEEE Trans. Parallel Distrib. Syst. 2(4):452-471 (1991).
7. Paul Feautrier, Some efficient solutions to the affine scheduling problem, Part I, one-dimensional time, IJPP 21(5):xx-xx (October 1992).
8. Wayne Kelly and William Pugh, A unifying framework for iteration reordering transformations, IEEE First Int'l. Conf. Algorithms and Architectures for Parallel Processing (April 1995).
9. Daniel Lavery and Wen-mei Hwu, Unrolling-based optimizations for modulo scheduling, 28th Int'l. Symp. Microarchit., pp. 126-141 (December 1995).
10. Stephanie Coleman and Kathryn S. McKinley, Tile size selection using cache organization and data layout, Progr. Lang. Design and Implementation (June 1995).
11. Vivek Sarkar, Guang R. Gao, and Shaohua Han, Locality analysis for distributed shared-memory multiprocessors, Lang. Compilers for Parallel Computing (1996).
12. Dennis Gannon and Ko-Yang Wang, Applying AI Techniques to Program Optimization for Parallel Computers, Chap. 12, McGraw Hill Co. (1989).
13. Michael E. Wolf, Dror Maydan, and Ding-Kai Chen, Combining loop transformations considering caches and scheduling, 29th Int'l. Symp. Microarchit. (December 1996).
14. Michael J. Wolfe, Iteration space tiling for memory hierarchies, Parallel Processing for Sci. Comput., pp. 357-361 (1987).
15. J. Ramanujam and P. Sadayappan, Tiling multidimensional iteration spaces for nonshared memory machines, Supercomputing (November 1991).
16. David A. Padua and Michael J. Wolfe, Advanced compiler optimizations for supercomputers, Commun. ACM 29(12):1184-1201 (December 1986).
17. Dennis Gannon, William Jalby, and Kyle Gallivan, Strategies for cache and local memory management by global program transformation, J. Parallel and Distrib. Comput., Vol. 5, No. 5 (October 1988).
18. François Irigoin and Rémi Triolet, Supernode partitioning Principles of Progr. Lang., pp. 319-328 (January 1988).
19. Michael J. Wolfe, More iteration space tiling, Supercomputing, pp. 655-664 (1989).
20. Monica S. Lam, Edward E. Rothberg, and Michael E. Wolf, The cache performance and optimizations of blocked algorithms, ASPLOS-IV , Palo Alto, California (April 1991).
21. Utpal Banerjee, Unimodular transformations of double loops, in Progr. Lang. Compilers for Parallel Computing, Irvine, California (August 1990).
22. Ken Kennedy and Kathryn S. McKinley, Optimizing for parallelism and data locality, Intl. Conf. Supercomputing (July 1992).
23. Jeanne Ferrante, Vivek Sarkar, and Wedy Thrash, On estimating and enhancing cache effectiveness, Lang. Compilers for Parallel Computing (1991).
24. Anant Agarwal, David Kranz, and Venkat Natarajan, Automatic partitioning of parallel loops and data arrays for distributed shared memory multiprocessors, Int'l. Conf. Parallel Computing (1993).
25. Vivek Sarkar and Radhika Thekkath, A general framework for iteration-reordering loop transformations, Technical Summary, Progr. Lang. Design and Implementation (1992).
26. Steve Carr, Combining optimization for cache and instruction-level parallelism, PACT '96, pp. 238-247 (1996).
27. Ken Kennedy and Kathryn S. McKinley, Maximizing loop parallelism and improving data locality via loop fusion and distribution, Lang. Compilers for Parallel Computing (1993).
28. Jeff Bilmes, Krste Asanović, Chee-Whye Chin, and Jim Demmel, Optimizing matrix multiply using PHiPAC: a portable, high-performance, ANSI C coding methodology, Intl. Conf. Supercomputing (1997).
29. Larry Carter, Jeanne Ferrante, Susan Flynn Hummel, Bowen Alpern, and Kang Su Gatlin, Hierarchical tiling: A methodology for high performance, Technical Report CS96-508, UCSD, Department of Computer Science and Engineering (November 1996).
30. Doug Burger and Todd Austin, The SimpleScalar architectural research tool set, Version 2.0, http://www.cs.wisc.edu/m̃scalar/simplescalar.html
31. Karin Högstedt, Larry Carter, and Jeanne Ferrante, Determining the idle time of a tiling, Principles of Progr. Lang. (1997).
32. Larry Carter, Jeanne Ferrante, and S. Flynn Hummel, Hierarchical tiling for improved superscalar performance, Int'l. Parallel Processing Symp. (April 1995).