A fast algorithm for area minimization of slicing floorplans

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 12, 1996, Pages 1525-1532

  Shi, Weiping ^a  

^a UNIVERSITY OF NORTH TEXAS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; INTEGRATED CIRCUIT LAYOUT; OPTIMIZATION; SET THEORY; TREES (MATHEMATICS); VLSI CIRCUITS;

HORIZONTAL LINE SEGMENTS; SPACE COMPLEXITY; TIME COMPLEXITY; VERTICAL LINE SEGMENTS;

ALGORITHMS;

EID: 0030379336     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.552085     Document Type: Article

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