Logic and memory with nanocell circuits

IEEE Transactions on Electron Devices

Volumn 50, Issue 9, 2003, Pages 1865-1875

  Husband, Christopher P ^a   Husband, Summer M ^a   Daniels, Jonathan S ^a,b   Tour, James M ^a  

^a RICE UNIVERSITY   (United States)

^b IEEE   (United States)

Author keywords

Latching; Logic; Memory; Molecular electronics; Nanocell; Self assembly

Indexed keywords

CURRENT VOLTAGE CHARACTERISTICS; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT MANUFACTURE; LOGIC GATES; LOGIC PROGRAMMING; NANOTECHNOLOGY; NEGATIVE RESISTANCE; SELF ASSEMBLY; TECHNOLOGICAL FORECASTING;

MOLECULAR ELECTRONICS; NANOCELL CIRCUITS; NEGATIVE DIFFERENTIAL RESISTANCE;

MICROELECTRONICS;

EID: 0041409588     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.815860     Document Type: Article

References (19)

1. Int. Technol. Roadmap for Semiconductors: 2001, Semiconductor Industry Assoc., San Jose, CA, 2001.
2. R. F. Service, "Nanocomputing. Assembling nanocircuits from the bottom up," Science, vol. 293, pp. 782-785, 2001.
3. J. R. Heath, P. J. Kuekes, G. R. Snider, and R. S. Williams, "A defect-tolerant computer architecture: opportunities for nanotechnology," Science, vol. 280, p. 1716, 1998.
4. S. C. Goldstein and M. Budiu, "NanoFabrics: spatial computing using molecular electronics," in Proc. ISCA, 2001.
5. G. L. Snider, A. O. Orlov, I. Amlani, X. Zuo, G. H. Bernstein, C. S. Lent, J. L. Merz, and W. Porod, "Quantum-dot cellular automata: review and recent experiments (invited)," J. Appl. Phys., vol. 85, p. 4283, 1999.
6. J. M. Tour, W. L. VanZandt, C. P. Husband, S. M. Husband, L. S. Wilson, P. D. Franzon, and D. P. Nackashi, "Nanocell logic gates for molecular computing," IEEE Trans. Nanotechnol., vol. 1, pp. 100-109, June 2002.
7. J. Chen, W. Wang, M. A. Reed, A. M. Rawlett, and J. M. Tour, "Room-temperature negative differential resistance in nanoscale molecular junctions," Appl. Phys. Lett., pp. 1224-1226, 2000.
8. ____, "Room temperature negative differential resistance in nanoscale molecular junctions," in Proc. Mater. Res. Soc. Symp., 2001, p. 5.
9. A. Ulman, "Formation and structure of self-assembled monolayers," Chem. Rev., vol. 96, pp. 1533-1554, 1996.
10. M. A. Reed, C. Zhou, C. J. Muller, T. Burgin, and J. M. Tour, "Conductance of a molecular junction," Science, pp. 252-254, 1997.
11. J. Chen, M. A. Reed, A. M. Rawlett, and J. M. Tour, "Large on-off ratios and negative differential resistance in a molecular electronic device," Science, vol. 286, p. 1550, 1999.
12. M. A. Reed, J. Chen, A. M. Rawlett, D. W. Price, and J. M. Tour, "Molecular random access memory cell," Appl. Phys. Lett., vol. 78, pp. 3735-3737, 2001.
13. D. P. Bertsekas and J. N. Tsitsiklis, Neuro-Dynamic Programming. Belmont, MA: Athena Scientific, 1996.
14. D. E. Goldberg, Genetic Algorithms in Search, Optimization, and Machine Learning. Reading, MA: Addison Wesley, 1989.
15. J. M. Tour, Molecular Electronics: Commercial Insights, Chemistry, Devices, Architecture and Programming. River Edge, NJ: World Scientific, 2002.
16. E. Goto, "The parametron: a digital computing element which utilizes parametric oscillation," Proc. IRE, vol. 47, p. 1304, 1959.
17. R. H. Mathews, J. P. Sage, T. C. Sollner, S. D. Calawa, C. Chen, L. J. Mahoney, P. A. Maki, and K. M. Molvar, "A new RTD-FET logic family," Proc. IEEE, vol. 87, pp. 596-605, Apr. 1999 (see also 15).
18. D. L. Allara, M. A. Reed, and J. M. Tour, presented at the DARPA Research Conf., 2001.
19. D. Berzon and T. J. Fountain, "A memory design in QCA's using the squares formalism," in Proc. Ninth Great Lakes Symp. VLSI, Ann Arbor, MI, 1999.