Analysis of on-chip spiral inductors using the distributed capacitance model

IEEE Journal of Solid-State Circuits

Volumn 38, Issue 6, 2003, Pages 1040-1044

  Wu, Chia Hsin ^a   Tang, Chih Chun ^a   Liu, Shen Iuan ^a  

^a NATIONAL TAIWAN UNIVERSITY   (Taiwan)

Author keywords

Distributed capacitance model (DCM); Miniature three dimensional inductor; On chip inductor; Stacked inductor

Indexed keywords

APPROXIMATION THEORY; CAPACITANCE; CMOS INTEGRATED CIRCUITS; INDUCTANCE; Q FACTOR MEASUREMENT; VOLTAGE DISTRIBUTION MEASUREMENT;

METAL TRACKS;

ELECTRIC INDUCTORS;

EID: 0038718677     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2003.811965     Document Type: Article

References (17)

1. D. K. Shaffer and T. H. Lee, "A 1.5-V 1.5-GHz CMOS low noise amplifier," IEEE J. Solid-State Circuits, vol. 32, pp. 745-759, May 1997.
2. A. Hajimiri and T. H. Lee, "A general theory of phase noise in electrical oscillators," IEEE J. Solid-State Circuits, vol. 33, pp. 179-194, Feb. 1998.
3. C. P. Yue and S. S. Wong, "On-chip spiral inductors with patterned ground shields for Si-based RF ICs," IEEE J. Solid-State Circuits, vol. 33, pp. 743-752, May 1998.
4. H. M. Greenhouse, "Design of planar rectangular microelectronic inductors," IEEE Trans. Parts, Hybrids, Packag., vol. PHP-10, pp. 101-109, June 1974.
5. S. S. Mohan, M. M. Hershenson, S. P. Boyd, and T. H. Lee, "Simple accurate expressions for planar spiral inductances," IEEE J. Solid-State Circuits, vol. 34, pp. 1419-1424, Oct. 1999.
6. A. M. Niknejad and R. G. Meyer, Design, Simulation and Applications of Inductors and Transformers for Si RF ICs. Boston, MA: Kluwer, 2000.
7. S. Jenei, B. K. J. C. Nauwelaers, and S. Decoutere, "Physics-based closed-form inductance expression for compact modeling of integrated spiral inductors," IEEE J. Solid-State Circuits, vol. 37, pp. 77-80, Jan. 2002.
8. A. Zolfaghari, A. Chan, and B. Razavi, "Stacked inductors and transformers in CMOS technology," IEEE J. Solid-State Circuits, vol. 36, pp. 620-628, Apr. 2001.
9. C. C. Tang, C. H. Wu, and S. I. Liu, "Miniature 3-D inductors in standard CMOS process," IEEE J. Solid-State Circuits, vol. 37, pp. 471-480, Apr. 2002.
10. C. P. Yue, C. Ryu, J. Lau, T. H. Lee, and S. S. Wong, "A physical model for planar spiral inductors on silicon," in IEEE IEDM Dig. Tech. Papers, 1996, pp. 155-158.
11. J. Crols, P. Kinget, J. Craninckx, and M. Steyaert, "An analytical model of planar inductors on lowly doped silicon substrates for high-frequency analog design up to 3 GHz," in Symp. VLSI Circuits Dig. Tech. Papers, 1996, pp. 28-29.
12. "UMC 0.5-μm mixed-signal (2P2M, 5.0-V) SPICE models," UMC Co. Ltd., Doc. G-03-MIXEDMODE50-5V-2P2M-PSUB, Ver. 2.2.
13. "TSMC 0.35 μm logic suicide (1P4M, 3.3V) SPICE models," Taiwan Semiconductor Manufacturing Co., Hsin-Chu, Taiwan, R.O.C., Doc. TA-1095-6002.
14. "TSMC 0.25 μm mixed-signal salicide (1P5M, 2.5V/3.3V) SPICE models," Taiwan Semiconductor Manufacturing Co., Hsin-Chu, Taiwan, R.O.C., Doc. TA-10A2-4002.
15. "TSMC 0.18 μm mixed-signal salicide (1P6M, 1.8V/3.3V) SPICE models," Taiwan Semiconductor Manufacturing Co., Hsin-Chu, Taiwan, R.O.C., Doc. T-018-MM-SP-002.
16. P. Arcioni, R. Castello, G. De Astis, E. Sacchi, and F. Svelto, "Measurement and modeling of Si integrated inductors," IEEE Trans. Instrum. Meas., vol. 47, pp. 1372-1378, Oct. 1998.
17. K. B. Ashby, I. A. Koullias, W. C. Finley, J. J. Bastek, and S. Moinian, "High Q inductors for wireless applications in a complementary silicon bipolar process," IEEE J. Solid-State Circuits, vol. 31, pp. 4-9, Jan. 1996.