Unified functional decomposition via encoding for FPGA technology mapping

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 9, Issue 2, 2001, Pages 251-260

  Jiang, Jie Hong ^b   Jou, Jing Yang ^a,c   Huang, Juinn Dar ^d  

^a IEEE

^b UNIVERSITY OF CALIFORNIA   (United States)

^c NATIONAL CHIAO TUNG UNIVERSITY   (Taiwan)

^d U Optronics Corporation   (Taiwan)

Author keywords

Compatible class encoding; FPGA; Functional decomposition; Technology mapping

Indexed keywords

ALGORITHMS; ELECTRIC NETWORK SYNTHESIS; ENCODING (SYMBOLS); FUNCTIONS; GRAPH THEORY; POLYNOMIAL APPROXIMATION; TABLE LOOKUP;

BINARY DECISION DIAGRAMS; COMPATIBLE CLASS ENCODING; FUNCTIONAL DECOMPOSITION; LOGIC SYNTHESIS; TECHNOLOGY MAPPING;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0035301376     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.924031     Document Type: Article

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