Resist trimming technique in CF4/O2 high-density plasmas for sub-0.1 μm MOSFET fabrication using 248-nm lithography

Microelectronic Engineering

Volumn 65, Issue 4, 2003, Pages 394-405

  Sin, Chian Yuh ^a,b   Chen, Bing Hung ^c   Loh, W L ^b   Yu, J ^b   Yelehanka, P ^b   Chan, L ^b  

^a NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^b CHARTERED SEMICONDUCTOR MANUFACTURING LTD   (Singapore)

^c NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

248 nm lithography; CF4 O2; Critical dimension (CD); Polycrystalline silicon (polysilicon); Polysilicon gate; Resist trimming

Indexed keywords

ETCHING; LITHOGRAPHY; PLASMAS; POLYSILICON; TRANSISTORS; TRIMMING;

MICROLOADING EFFECT;

MOSFET DEVICES;

EID: 0038637780     PISSN: 01679317     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0167-9317(03)00015-7     Document Type: Article

References (15)

1. Peters L. Ramping the 0.13 μm generation. Semiconductor Int. 24:(1):2001;56-68.
2. M Rothschild A.R., Forte R., Kunz R., Pamlateer S.C., Sedlacek J.H.C. Lithography at a wavelength of 193 nm. IBM J. Res. Dev. 41:(1/2):1997;49.
3. Baker D.C., Zheng T., Takemoto C.H., Sethi S., Gabriel C., Scott G.S. 0.12 μm logic process using 248 nm step-and-scan system. Proc. of SPIE 3999 :2000;294-304.
4. Burmester R., Winnerl J., Neppl F. Realization of Deep-Submicron MOSFETS by Lateral Etching. Microelectronic Eng. 13:(1-4):1991;473-476.
5. z film as an ARC and hardmask. 1997 Symposium on VLSI Technology: Digest of Technical Papers, 131, Japan Society of Applied Physics, Japan :1997.
6. W. Yang, L. Shen, Method for trimming a photoresist pattern line for memory gate etching, US Patent, 6,372,651 (2002).
7. Ono M., Saito M., Yoshitomi T., Fiegna C., Ohguro T., Iwai H. Fabrication of sub-50-nm gate length n-metal-oxide-semiconductor field effect transistors and their electrical characteristics. J. Vac. Sci. Technol. B. 13:(4):1995;1740.
8. Ono M., Saito M., Yoshitomi T., Fiegna C., Ohguro T., Iwai H. A 40-nm gate length n-MOSFET. IEEE Trans Electronic Devices. 42:(10):1995;1822-1830.
9. Chung J., Jeng M.-C., Moon J.E., Wu A.T., Chan T.Y., Ko P.K., Hu C.M. Deep-submicrometer MOS device fabrication using a photoresist-ashing technique. IEEE Electron. Device Lett. 9:(4):1988;186.
10. 2. Jap. J. Appl. Phys. 37:(4B):1998;2369-2372.
11. 2 plasmas for sub-0.1 μm device fabrication. J. Vac. Sci. Technol. B. 20:(5):2002;1974-1981.
12. Montgomery D.C. Design and Analysis of Experiments. 5th Edition :2001;John Wiley, New York.
13. Keller J.H., Forster J.C., Barnes M.S. Novel Radio-Frequency Induction Plasma Processing Techniques. J. Vac. Sci. Technol. A. 11:(5):1993;2487.
14. 4 addition on downflow ashing under atmospheric pressure. Jap. J. Appl. Phys. I. 38:(6A):1999;3731.
15. Sze S.M. Semiconductor Devices, Physics and Technology. 2nd Edition :2002;John Wiley, New York.