MTCMOS with Outer Feedback (MTOF) flip-flops

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2003, Pages

  Stan, Mircea R ^a   Barcella, Marco ^a  

^a UNIVERSITY OF VIRGINIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC POTENTIAL; FLIP FLOP CIRCUITS; LEAKAGE CURRENTS; POWER SUPPLY CIRCUITS; TRANSISTORS;

MULTI-THRESHOLD CMOS (MTCMOS);

CMOS INTEGRATED CIRCUITS;

EID: 0038420699     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

1. Device Group at UC Berkeley, "Berkeley predictive technology model," http://www-device.EECS.Berkeley.EDU/̃ptm/.
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3. Mircea R. Stan, "Optimal voltages and sizing for low power," in VLSI Design Conference, Goa, India, Jan. 1999.
4. Mutoh, S. et al., "A IV power supply high-speed digital circuit technology with multithreshold voltage CMOS," IEEE Journal of Solid-State Circuits, vol. 30, no. 8, pp. 847-854, Aug. 1995.
5. Mutoh, S. et al., "A IV multi-threshold voltage CMOS DSP for mobile phone application," IEEE Journal of Solid-State Circuits, vol. 31, no. 11, pp. 1795-1801, Nov. 1996.
6. J. Kao, A. Chandrakasan, and D. Antoniadis, "Transistor sizing issues and tool for multi-threshold CMOS technology," in Design Automation Conference, Anaheim, CA, June 1997.
7. M. R. Stan and J, Jasmin, "Multi-threshold flip-flop circuit having an outside feedback," 2000, U.S. Patent pending.
8. V. Stojanovic and V. G. Oklobdzija, "Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems," IEEE Journal of Solid-State Circuits, pp. 536-548, Apr. 1999.