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Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 42, Issue 4 B, 2003, Pages 1999-2003

Grain-boundary related hot carrier degradation mechanism in low-temperature polycrystalline silicon thin-film transistors

(5) Yoshida, Toshiyuki a Ebiko, Yoshiki b Takei, Michiko b Sasaki, Nobuo b Tsuchiya, Toshiaki b

a SHIMANE UNIVERSITY (Japan)

b FUJITSU LABORATORIES LTD (Japan)

Author keywords

Degradation mechanism; Grain boundary; Hot carrier; LT poly Si TFT

Indexed keywords

CARRIER CONCENTRATION; DEGRADATION; ELECTRIC RESISTANCE; ELECTRON TRAPS; GRAIN BOUNDARIES; HOT CARRIERS; INTERFACES (MATERIALS); LOW TEMPERATURE EFFECTS; PLASMA ENHANCED CHEMICAL VAPOR DEPOSITION; SEMICONDUCTING SILICON; THRESHOLD VOLTAGE;

CARRIER TRAPS; DRAIN CURRENTS; HOT CARRIER STRESS; POTENTIAL BARRIER; STRESS INDUCED RESISTANCE;

THIN FILM TRANSISTORS;

EID: 0038348023 PISSN: 00214922 EISSN: None Source Type: Journal
DOI: 10.1143/jjap.42.1999 Document Type: Article

Times cited : (17)

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