Deriving logic systems for path delay test generation

IEEE Transactions on Computers

Volumn 47, Issue 8, 1998, Pages 829-846

  Bose, Soumitra ^a,b   Agrawal, Prathima ^a,c   Agrawal, Vishwani D ^a,b  

^a IEEE   (United States)

^b LUCENT TECHNOLOGIES   (United States)

^c AT AND T LABS RESEARCH   (United States)

Author keywords

Delay testing; Digital test; Multivalued logic; Path delay faults; Simulation; Timing analysis

Indexed keywords

EID: 0038322300     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.707585     Document Type: Article

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