Gate-source-drain architecture impact on DC and RF performance of sub-100-nm elevated source/drain NMOS transistors

IEEE Transactions on Electron Devices

Volumn 50, Issue 3, 2003, Pages 610-617

  Jeamsaksiri, Wutthinan ^a   Jurczak, Malgorzata ^a   Grau, Lluís ^a,b   Linten, Dimitri ^a,c   Augendre, Emmanuel ^a   De Potter, Muriel ^a   Rooyackers, Rita ^a   Wambacq, Piet ^a   Badenes, Gonçal ^a,d  

^a IMEC   (Belgium)

^b Intel Ireland Ltd   (Ireland)

^c VRIJE UNIVERSITEIT BRUSSEL   (Belgium)

^d ICFO INSTITUT DE CIENCIES FOTONIQUES   (Spain)

Author keywords

Elevated source drain; Ion implantation; Low noise amplifier (LNA); RF CMOS; Silicide thickness

Indexed keywords

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC CONDUCTIVITY; ELECTRIC RESISTANCE; EPITAXIAL GROWTH; GATES (TRANSISTOR); ION IMPLANTATION; MOSFET DEVICES; SEMICONDUCTING SILICON COMPOUNDS; SUBSTRATES; TRANSCONDUCTANCE;

COBALT SILICIDE; DEEP SOURCE-DRAIN IMPLANT PROCESS; GATE-SOURCE-DRAIN ARCHITECTURE; JUNCTION LEAKAGE; LOW NOISE AMPLIFIER; SELECTIVE EPITAXIAL GROWTH;

SEMICONDUCTOR DEVICE MANUFACTURE;

EID: 0038236498     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2003.810478     Document Type: Article

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