MVL circuit design and characterization at the transistor level using SUS-LOC

Proceedings of The International Symposium on Multiple-Valued Logic

Volumn , Issue , 2003, Pages 105-110

  Kinvi Boh, E ^a   Aline, M ^a   Sentieys, O ^a   Olson, Edgar D ^b  

^a INRIA   (France)

^b EDO LLC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER HARDWARE DESCRIPTION LANGUAGES; COMPUTER SIMULATION; ELECTRIC INVERTERS; THRESHOLD VOLTAGE;

LOGIC TERNARY FUNCTIONS; MULTIPLE VALUED LOGIC; SUPPLEMENTARY SYMMETRICAL LOGIC CIRCUIT STRUCTURE;

LOGIC DESIGN;

EID: 0038157134     PISSN: 0195623X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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