The use of arithmetic operators in a self-restored current-mode CMOS multiple-valued logic design architecture

Proceedings of The International Symposium on Multiple-Valued Logic

Volumn , Issue , 2001, Pages 100-105

  Teng, H Y ^a   Bolton, R J ^a  

^a UNIVERSITY OF SASKATCHEWAN   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN FUNCTIONS; CMOS INTEGRATED CIRCUITS; DIGITAL ARITHMETIC; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL OPERATORS;

MULTIPLE VALUED LOGIC (MVL) DESIGNS;

LOGIC CIRCUITS;

EID: 0034821199     PISSN: 0195623X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)

1. A self-restored current- mode CMOS multiple-valued logic design architecture
2. A minimization technique for multiple-valued logic systems
3. CMOS multiple-valued logic design - Part I: Circuit implementation