An effective current source cell model for VDSM delay calculation

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2001-January, Issue , 2001, Pages 296-300

  Korshak, Alexander ^a   Lee, Jyh Chwen ^a  

^a SYNOPSYS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CYTOLOGY;

CELL MODEL; CURRENT SOURCES; DELAY CALCULATION; DIGITAL CELLS; EFFECTIVE CAPACITANCE; NEW APPROACHES; TRANSITION TIME;

CELLS;

EID: 84949968485     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2001.915246     Document Type: Conference Paper

References (4)

1. C.L. Ratzlaff, S. Pullela, and L. T. Pillage, "Modeling the RC-interconnect effects in a hierarchical timing analyzer", 1992 Custom Integrated Circuits Conference, Boston, MA, 1992.
2. F. Dartu, N. Menezes, and L. T. Pillage, "Modeling the "Effective Capacitance" for the RC Interconnect of CMOS Gates", IEEE Trans. Computer-Aided Design, Vol. 13, pp. 1526-1535, 1994.
3. J. Qian, S. Pullela, and L. T. Pileggi, "Performance Computation for Precharacterized CMOS Gates with RC Loads", IEEE Trans. Computer-Aided Design, Vol. 15, pp. 544-553, 1996.
4. F. Dartu and L. T. Pileggi, "Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling", DAC 97, Anaheim, CA, pp. 46-51.