Investigation of fundamental technology for 3D assembly

Proceedings of SPIE - The International Society for Optical Engineering

Volumn 4931, Issue , 2002, Pages 348-353

  Murayama, Kei ^a   Higashi, Mitsutoshi ^a   Shimizu, Mitsuharu ^a  

^a SHINKO ELECTRIC INDUSTRIES CO LTD   (Japan)

Author keywords

Embedded components; Interconnection; Stress relief; Three dimensional; Wafer thinning

Indexed keywords

BONDING; INTELLECTUAL PROPERTY; SEMICONDUCTOR DEVICE MANUFACTURE; SILICON WAFERS; SUBSTRATES; THREE DIMENSIONAL; ULTRASONIC APPLICATIONS;

LOW STRESS INTERCONNECTION; SEMICONDUCTOR PACKAGING TECHNIQUE; STRESS RELEIF PROCESS; SUBSTRATE PROCESS; ULTRASONIC BONDING; WAFFER THINNER TECHNIQUE;

ELECTRONICS PACKAGING;

EID: 0036448277     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. URL: http://www.nttdocomo.co.jp/info/release/
2. K. Murayama, M. Higashi, "Development of Ultra thin Package", proceeding of the MES2000, Osaka, Japan pp267-270, 2000.
3. Takashi Kurihara, S.Mizuno, K. Miyazawa, S. Sato, M.Horiuchi, "Super thin package for 3-dimensional assembly", proceeding of the MES2000,Osaka, Japan p271-274
4. T.Abe, "silicon", baifukan Publishers, second edition, Tokyo, Chapter4, 1994
5. K. Arita, T. Iwai, H.Haji, E. Nitta, Y. Koma "Development of plasma stress relief technology in wafer thinning process", proceeding of the MES2001, Osaka, Japan, p175-178
6. Ryoichi Kajiwara, et al. "Ultrasonic Flip Chip Bonding Technology for LSI Chip with High Pin Counts", proceeding of 7th Symposium on "Microjoining and Assembly Technology in Electronics", Yokohama, Japan, February 1-2, 2001, pp161-166.
7. K.Higashi, K. Ushirakawa, K. Tomita, "Development of Flip-Chip Mounting process by Metallic Joint Which Uses Supersonic Ultrasonic Wave Energy", ICEP proceedings p478-483
8. N. Mashino, K. Murayama, T. Kurihara, M. Higashi, M. Shimizu, "Development of Wireing Technologies for Chip Level 3-Domentional Assembly", proceeding of the MES2001, Osaka, Japan, p327-330
9. S. Komatsu, Y. Sugaya, T. Asahi, Y. Yamamoto, S. Nakatani, "The Development of Interconnection of Super Integrated Module", proceeding of the MES2001, Osaka, Japan, p311-314