A low-power architecture for maximum a posteriori decoding

Conference Record of the Asilomar Conference on Signals, Systems and Computers

Volumn 1, Issue , 2002, Pages 47-51

  López Vallejo, Marisa ^a   Mujtaba, Syed Aon ^b   Lee, Inkyu ^c  

^a UNIVERSIDAD POLITÉCNICA DE MADRID   (Spain)

^b AGERE SYSTEMS   (United States)

^c Korea University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; ERROR ANALYSIS; TURBO CODES;

POWER DISSIPATION;

DECODING;

EID: 0037967628     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

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