Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients

Proceedings - Design Automation Conference

Volumn , Issue , 2002, Pages 399-404

  Badaroglu, Mustafa ^a   Tiri, Kris ^a   Donnay, Stéphane ^a   Wambacq, Piet ^a   Verbauwhede, Ingrid ^a   Gielen, Georges ^a   De Man, Hugo ^a  

^a IMEC   (Belgium)

Author keywords

Clock distribution networks; di dt noise; Low noise digital design; Substrate noise; Supply current shaping and optimization

Indexed keywords

CLOCK TREE OPTIMIZATION; SUPPLY CURRENT TRANSIENTS;

DIGITAL CIRCUITS; ELECTRIC SWITCHES; OPTIMIZATION; SPURIOUS SIGNAL NOISE; TRANSIENTS;

CMOS INTEGRATED CIRCUITS;

EID: 0036054409     PISSN: 0738100X     EISSN: None     Source Type: Journal    
DOI: 10.1109/DAC.2002.1012658     Document Type: Article

References (13)

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